topic: synchronization/coherency issues in multi-core architecture. e.g., transactional memory

meeting next time: 12/22 AM 11:00

Oral presentation: 12/31 PM:15:30

term report due date: 1/21

1. transaction memory

 宗慶, 文昌

2. token coherence, ring based ... and some new coherence protocol

 文隆, 雋中

3. 把multi-processor的東西修改後,加在cmp上

 皓翔, 俞任

Paper referenced:

proximity-aware_directory-based_coherence_for_multi-core_processor_architectures.pdf

● Synchronization state buffer: supporting efficient fine-grain synchronization on many-core architectures ISCA’07

● Coherence decoupling: making use of incoherence ASPLOS’04

a survey of cache coherence schemes for multiprocessors, 1990

● interconnect-aware coherence protocols for chip multiprocessors, 2006

● cache coherence in large-scale shared-memory multiprocessors: issues and comparisons, 1993

● transactional collection classes, 2007

● transactional memory coherence and consistency, 2004

● split private and shared L2 cache architecture for snooping-based cmp, 2007


Example papers:

1.a_survey_of_research_oand_practices_of_network-on-chip.pdf

2.2000_p115-benini_system-level_power_optimization_techniques_and_tools.pdf

 
aca_final_presentation_2007.txt · Last modified: 2010/05/22 09:20 (external edit)
 
Recent changes RSS feed Creative Commons License Donate Powered by PHP Valid XHTML 1.0 Valid CSS Driven by DokuWiki