Presenter

王俊文

Title

A NAND Flash Memory File Cache for Low Power Web Servers

Abstraction

We propose an architecture that uses NAND flash memory to reduce main memory power in web server platforms. Our architecture uses a two level file buffer cache composed of a relatively small DRAM, which includes a primary file buffer cache, and a flash memory secondary file buffer cache. Compared to a conventional DRAM-only architecture, our architecture consumes orders of magnitude less idle power while remaining cost effective. This is a result of using flash memory, which consumes orders of magnitude less idle power than DRAM and is twice as dense. The client request behavior in web servers, allows us to show that the primary drawbacks of flash memory—endurance and long write latencies—can easily be overcome. In fact the wearlevel aware management techniques that we propose are not heavily used.

Paper

Presentation

 
flashcache/a_nand_flash_memory_file_cache_for_low_power_web_servers.txt · Last modified: 2010/05/22 09:20 (external edit)
 
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